ALICEADVANCED INTELLIGENCE / AUSTERE EDGERESEARCH DOSSIER

11F83 / SYSTEM DOSSIER

ALICE.
Intelligence at the austere edge.

Offline computation. Bounded execution. Evidence-bearing control. A resource-adaptive runtime for severe power, memory, and connectivity constraints.

Inspect signal & sourcesView field briefs 04 FILES
MEMORY MODEL
ZERO HEAP
NUMERIC PATH
Q16.16
BENCH LATENCY¹
18.5 μs
DEVELOPMENT
RESEARCH / TRL 3¹

¹ Source-reported MCU bench results. Detection-to-execution latency; physical integration is proposed. Review evidence

ALICE A-Prime subject portrait with technical telemetry overlays
SUBJECT / ALICE A-PRIMEVISUAL IDENTITY / CONCEPT

SIGNAL / EVIDENCE BOUNDARY

Every claim.
A visible boundary.

Recover the architecture, inspect the source, and see the next verification step.

REVIEWED 07 OCT 2026 · 9 SOURCE RECORDS
01Inspect evidenceScope, source, open questions02Trace architectureOffline work to edge execution03Watch field briefsFour embedded research videos04Review provenanceIdentity and SIG_V3 status
REPORTED / S017.79 KB

Full math + control stack

Flash · source-reported MCU bench

REPORTED / S01348 B

Static SRAM

Source-reported · zero heap design

REPORTED / S0118.5 μs

Detection to execution

Reported watchdog interrupt latency

REPORTED / S01TRL 3 / 4

Reported / proposed

Bench algorithms / physical integration

Proposal to effect

ARCHITECTURE / S03–S05
  1. 01 / IRISObserve & normalize

    Identity · sequence · age · confidence

  2. 02 / ALICEBound state & propose

    State set · uncertainty · capability

  3. 03 / IRACheck authority

    Installed envelope · fresh witnesses · policy

    ✓ Permit within scope? Hold for evidence✕ Deny outside scope
  4. 04 / QSNvRecord result & gaps

    Receipt · postcondition · continuity epoch

OBSERVED ≠ INFERRED ≠ PREDICTED ≠ KNOWNRECOVER ≠ REPLICATE ≠ RESUME ≠ CONTINUE

SOURCE INDEX

Follow the claim to its source.

9 of 9 sources

S01 / REPORTEDDocument dated 17 Jul 2026

LRC concept paper

DARPA LRC Concept Paper (1)(2).pdf · §§3–4 · Table 2

Contribution
Offline derivation, Q16.16 execution, static allocation, and an MCU bench profile. Reports 7.79 KB flash, 348 B static SRAM, 18.5 μs detection-to-execution latency, and 10,000 injected-fault cycles.
Verification boundary
These are the paper's reported results. Raw test logs, firmware, timing traces, and an independent replication were not part of this source review. TRL 3 is reported; TRL 4 hardware integration is proposed. A <4 KB lookup structure is distinct from the 7.79 KB whole stack.
Used in this dossier
Runtime metrics · resource envelope · HLN timing scope
Source excerpt & provenance
Runtime execution consists solely of deterministic integer arithmetic and lookup operations.

Record identifies the reviewed document and section. A source-file checksum was not available in the extracted-text review.

SIG_V3 / PROVENANCE

Identity travels with the record.

The supplied Ed25519 token is abbreviated and the payload body is omitted. Verification is incomplete.

Declared type
ELF64 / x86_64
Signature status
INCOMPLETE SOURCE
Required to verify
Exact payload bytes, a complete detached signature, and a trusted signer public key.
Verification scope
A valid signature would authenticate specific bytes under a key; physical truth and action authority require separate evidence.
TEXT REFERENCE / PAYLOAD OMITTED
GEORGE NERO LINDSTROM, JR.
Chief Systems Architect | APD | CAGE: 11F83

SIG_V3
AUTH: Ed25519:6f8e7d...a2b1 (Detached Signature)
TYPE: ELF64/x86_64
DATA: [excerpt contains an omitted payload body]
END
Source text is displayed as an inert reference.

The source review records reported results, architecture decisions, and unresolved material separately.

01 / OPERATING PREMISE

Solve offline.
Execute within bounds.

ALICE relocates expensive numerical work to the design phase. Runtime checks operate on a constrained representation with explicit fallback conditions.

01DESIGN DOMAIN

Solve offline

Integrate complex behavior at design time, where compute, power, and verification are available.

02LATTICE DOMAIN

Encode geometry

Compile validated trajectories into bounded, pre-calculated geometric lookup structures.

03MISSION DOMAIN

Execute at the edge

Run deterministic fixed-point decisions without a solver, allocator, cloud path, or fragile runtime.

Σ

COMPLEXITY SHIFTReal-time numerical solvers → pre-calculated geometric lookups

OFFLINE SOLVE / BOUNDED RUNTIME

02 / RUNTIME ENVELOPE

Small runtime.
Explicit limits.

ALICE is not a smaller cloud stack. It is a different computational contract: bounded, inspectable, and designed to retain useful behavior as resources vanish.

ALICE lattice subject visualization
A-PRIME / LATTICE VIEWCONCEPT

MODELRESEARCH ARCHITECTURE

RF FRONT ENDPROPOSED INTEGRATION

HEAP0 B / DESIGN

GEO/01

Precomputed control geometry

Offline-derived trajectories are encoded as bounded lookup structures. Timing and coverage must be established for each deployed implementation.

FIXED-SIZE LOOKUP
MEM/02

Zero-heap execution

Static allocation and Q16.16 fixed-point arithmetic remove allocator failure modes and keep timing behavior legible.

0 B DYNAMIC
RF/03

Passive wake path

A 915 MHz front end can use ambient RF energy to wake the system before the primary communications path is energized.

75 nA TARGET
HLN/04

Neutral-state recovery

The High–Low Neutrality watchdog classifies state excursions, rejects corrupted transitions, and restores a known-stable state.

< 20 μs TARGET
FAB/05

Trusted legacy nodes

Mature 90–180 nm fabrication is a design objective. The concept paper reports 7.79 KB for the full math and control stack on its MCU bench.

7.79 KB / REPORTED
OPS/06

Degraded-mode autonomy

Retain bounded local behavior under link loss. Freshness, resource limits, policy expiry, and recovery conditions remain explicit.

BOUNDED LOCAL CONTROL

03 / EXECUTION PATH

Compile the geometry.
Check the boundary.

OFFLINE / 01

Numerical integration

Explore the full state space with high-resource solvers.

COMPILER / 02

Geometric encoding

Quantize validated paths into a static decision lattice.

EDGE / 03

Deterministic lookup

Execute fixed-point transitions within target-specific timing and resource limits.

GUARD / 04

HLN supervision

Validate state, neutralize faults, restore operation.

RUNTIME ATTRIBUTESOLVER-BASED APPROACHALICE TARGET
Control evaluationIterative / model-dependentGeometric lookup
Memory behaviorImplementation-dependentStatic / zero heap
ConnectivityImplementation-dependentBounded local execution
Fault responseRestart / degradeNeutralize / restore

04 / RESILIENT RECOVERY

Faults are events.
They do not become identity.

High–Low Neutrality treats anomalous state as a bounded excursion. When an invariant fails, the watchdog blocks propagation, enters a neutral state, and restores a validated operating frame. The LRC concept reports 18.5 μs detection-to-execution latency on its specified MCU bench; end-to-end recovery and continuity require separate validation.

DETECTIONINVARIANT-BASED
SAFE STATENEUTRAL LOCK
BENCH LATENCY18.5 μs / REPORTED
HLN // RECOVERY SEQUENCEILLUSTRATIVE
HHIGH
LLOW
NNEUTRAL
  1. 01

    SENSE State checksum diverges

    OBSERVATION
  2. 02

    CLASSIFY Excursion exceeds bound

    CHECK
  3. 03

    NEUTRALIZE Transition gate closes

    FALLBACK
  4. 04

    RESTORE Validated frame is evaluated

    REAUTHORIZE

05 / MISSION CONDITIONS

Designed around what fails first.

01

INTERMITTENT POWER

Resume from bounded state without rebuilding an application-scale runtime.

02

DENIED COMMUNICATIONS

Continue local decision logic when backhaul, cloud, or command links disappear.

03

RADIATION + NOISE

Detect invalid transitions and force a neutral state before corrupted behavior propagates.

04

CONSTRAINED SUPPLY

Run high-value logic on mature, inspectable, domestically accessible silicon.

LRC CONCEPT / SCOPE BY METRIC
7.79 KBSTACK / REPORTED
348 BSRAM / REPORTED
75 nACOMPARATOR / DESIGN
90–180 nmFABRICATION / GOAL
18.5 μsLATENCY / REPORTED

06 / FIELD TRANSMISSIONS

The architecture,
in motion.

Selected system briefs from the ALICE research archive.

PLAYBACK / ERIS-S1RESEARCH BRIEF
Open selected video
ACTIVE BRIEF

ERIS / Contested computation

Operational framing for preemptive edge control under adversarial and resource-constrained conditions.

TRANSMISSION INDEX04 FILES

07 / RESEARCH ARCHIVE

One architecture.
Eight technical threads.

A01

Adaptive Edge Runtime

RUNTIME ARCHITECTURE

Offline derivation, compact lookup structures, and fixed-point execution. See the architecture and LRC source record.

Review this thread
A02

Austere Edge Sovereignty

MISSION COMPUTE

Local computation under connectivity and resource constraints. Watch the Sovereign Computing brief.

Review this thread
A03

Extreme Edge Engineering

SYSTEM DESIGN

Power, memory, electrical faults, and silicon availability form distinct engineering boundaries.

Review this thread
A04

Evidence-bearing Authorization

CONTROL BOUNDARY

ALICE proposes; IRA checks bounded authority. Composition coverage, witness generation, and target timing remain open verification work.

Review this thread
A05

Resilient Edge Computing

FAULT TOLERANCE

HLN supervises excursions and fallback. Recovery and identity continuity require separate evidence.

Review this thread
A06

Resilient Embedded Runtime

EMBEDDED SYSTEMS

A zero-heap design and Q16.16 arithmetic keep resource bounds explicit; hardware validation remains implementation-specific.

Review this thread
A07

Resource-Adaptive Runtime

RESOURCE GOVERNANCE

The LRC concept reports 7.79 KB flash and 348 B static SRAM. Lookup-table size and whole-stack size have different scope.

Review this thread
A08

Computing for Austere Environments

MEDIA BRIEFS

Four existing video briefs remain available with one shared player and a selectable index.

Review this thread

08 / PROGRAM INTERFACE

Bring the mission constraint.
We will start there.

ALICE is an active Niratech Corp. research architecture for deterministic, resilient intelligence at the austere edge.

Initiate technical exchange
GEORGE NERO LINDSTROM, JR.Chief Systems Architect | APD | CAGE: 11F83Review SIG_V3 provenance
NIRATECH CORPCAGE / 11F83UNITED STATESR&D / 2026